Semiconductor Manufacturing by Elmer Epistola

Semiconductor Manufacturing

by Elmer Epistola

They're everywhere. From appliances to space ships, semiconductors have pervaded every fabric of our society. Nowadays, semiconductor devices allow machines to talk to us, and probably even understand us. They do our jobs, go where man has never gone before, and help us explore and utilize the universe around us. So overwhelming is the power of computing and signal processing today that it's difficult to believe how these can come from sand.

This world has indeed been reinvented simply by purifying sand, making it flat, and adding materials to it. This magical process of building integrated circuits from sand is now referred to as semiconductor manufacturing.

Semiconductor manufacturing consists of the following steps:

1) production of silicon wafers from very pure silicon ingots;

2) fabrication of integrated circuits onto these wafers;

3) assembly of every integrated circuit on the wafer into a finished product; and

4) testing and back-end processing of the finished products.

Wafer Fabrication

Wafer fabrication generally refers to the process of building integrated circuits on silicon wafers. Prior to wafer fabrication, the raw silicon wafers to be used for this purpose are first produced from very pure silicon ingots, through either the Czochralski (CZ) or the Float Zone (FZ) method. The ingots are shaped then sliced into thin wafers through a process called wafering.

A silicon wafer

The semiconductor industry has already advanced tremendously that there now exist so many distinct wafer fab processes, allowing the device designer to optimize his design by selecting the best fab process for his device. Nonetheless, all existing fab processes today simply consist of a series of steps to deposit special material layers on the wafers one at a time in precise amounts and patterns. Below is an example of what fabricating a simple CMOS integrated circuit on a wafer may entail.

The first step might be to grow a p-type epitaxial layer on the silicon substrate through chemical vapor deposition. A nitride layer may then be deposited over the epi-layer, then masked and etched according to specific patterns, leaving behind exposed areas on the epi-layer, i.e., areas no longer covered by the nitride layer. These exposed areas may then be masked again in specific patterns before being subjected to diffusion or ion implantation to receive dopants such as phosphorus, forming n-wells.

Silicon dioxide may then be grown thermally to form field oxides that isolate the n-wells from other parts of the circuit. This may be followed by another masking/oxidation cycle to grow gate oxide layers over the n-wells intended for p-channel MOS transistors later on. This gate oxide layer will serve as isolation between the channel and the gate of each of these transistors. Another mask and diffusion/implant cycle may then follow to adjust threshold voltages on other parts of the epi, intended for n-channel transistors later on.

Deposition of a polysilicon layer over the wafer may then be done, to be followed by a masking/etching cycle to remove unwanted polysilicon areas, defining the polysilicon gates over the gate oxide of the p-channel transistors. At the same time, openings for the source and drain drive-ins are made on the n-wells by etching away oxide at the right locations.

Another round of mask/implant cycle may then follow, this time driving in boron dopants into new openings of the n-wells, forming the p-type sources and drains. This may then be followed by a mask/implant cycle to form the n-type sources and drains of the n-channel transistors in the p-type epi.

The wafer may then be covered with phospho-silica glass, which is then subjected to reactive ion etching in specific patterns to expose the contact areas for metallization. Aluminum is then sputtered on the wafer, after which it is subjected to reactive ion etching, also in specific patterns, forming connections between the various components of the circuit.

The wafer may then be covered with glassivation as its top protective layer, after which a mask/etch process removes the glass over the bond pads.

Such is the process of wafer fabrication, consisting of a long series of mask/etch and mask/deposition steps until the circuit is completed.

Assembly

The process of putting the integrated circuit inside a package to make it reliable and convenient to use is known as semiconductor package assembly, or simply 'assembly'. Over the years, the direction of assembly technology is to develop smaller, cheaper, more reliable, and more environment-friendly packages. Just like wafer fabrication technology, assembly technology has advanced tremendously that there are now a multitude of packages to choose from.

Despite glaring differences between the various packages available in the industry today, all packages share some things in common. To name a few, all of them: 1) provide the integrated circuit with a structure to operate in; 2) protect the integrated circuit from the environment; 3) connect the integrated circuit to the outside world; and 4) help optimize the operation of the device.

In general, an assembly process would consist of the following steps: 1) die preparation, which cuts the wafer into individual integrated circuits or dice; 2) die attach, which attaches the die to the support structure (e.g., the leadframe) of the package; 3) bonding, which connects the circuit to the electrical extremities of the package, thereby allowing the circuit to be connected to the outside world; and 4) encapsulation (usually by plastic molding), which provides 'body' to the package of the circuit for physical and chemical protection.

Subsequent steps that give the package its final form and appearance (e.g., DTFS) vary from package to package. Steps like marking and lead finish give the product its own identity, improve reliability, and add an extra shine at that.

Assembly Links:

Wafer Backgrind → Die Preparation → Die Attach → Wirebonding → Die Overcoat →

→ Molding → Sealing → Marking → DTFS → Leadfinish

Test

Once assembled, the integrated circuit is ready to use. However, owing to the imperfection of this world, assembled devices don't always work. Many things can go wrong to make a device fail, e.g., the die has wafer fab-related defects, or the die cracked during assembly, or the bonds were poorly connected or not connected at all. Thus, prior to shipment to the customer, assembled devices must first be electrically tested.

Electrical testing of devices in big volumes must be done fast and inexpensively. Mass-production electrical testing therefore requires an automated system for doing the test. Equipment used to test devices are called, well, testers, and equipment used to handle the devices while undergoing testing are called, well, handlers. Tester/handler systems are also known as automatic test equipment (ATE).

Different products require different levels of sophistication in ATE requirements. Electrical testing of voltage reference circuits certainly don't require high-end ATE such as those used to test state-of-the-art microprocessors or digital signal processors. One area of electrical testing that continuously challenge engineers is building an ATE that can test the speed of new IC's that are much faster than what they can use in building their ATE's.

Software written for testing a device with an ATE is known as a test program. Test programs consist of a series of subroutines known as test blocks. Generally, each test block has a corresponding device parameter to test under specific conditions. This is accomplished by subjecting the device under test (DUT) to specific excitation and measuring the response of the device. The measurement is then compared to the pass/fail limits set in the test program. After the device is tested, the handler bins it out either as a reject or as a good unit.

After a lot is tested, it is subjected to other back-end processes prior to shipment to the customer. Tape and reel is the process of packing surface mount devices in tapes with pockets while this tape is being wound around a reel. Boxing and labeling is the process of putting the reels or tubes in shipment boxes, and labeling these shipment boxes in accordance with customer requirements.

Wafer Fab Links:

Incoming Wafers → Epitaxy → Diffusion → Ion Implant → Polysilicon → Dielectric →

→ Lithography/Etch → Thin Films → Metallization → Glassivation → Probe/Trim

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