Dynamic Random Access Memories; Dynamic RAMs, DRAMs

Dynamic Random Access Memories (DRAMs)

Random Access Memory (RAM) refers to a read/write memory device that can read data from or write data to any of its memory addresses, regardless of what memory address was last accessed for reading or writing. RAM comes in two major classifications: Dynamic RAM, or DRAM, and Static RAM, or SRAM.

DRAMs store data in cells that depend on capacitors, which need to be 'refreshed' continuously since they are not able to retain data indefinitely even if the device is continuously powered up. SRAMs, on the other hand, store data in flip-flops, which retain data without refreshing as long as the SRAM is powered up.

DRAMs provide more memory per unit chip area compared to SRAMs, mainly because of the much simpler structure of its storage element. Whereas an SRAM memory cell consists of 4 to 6 transistors, a DRAM memory cell consists of only a single transistor that is paired with a capacitor. The presence or absence of charge in the capacitor determines whether the cell contains a '1' or a '0'. This single-transistor configuration is commonly referred to as a 1-T memory cell.

A typical DRAM IC has address lines, data lines, and control lines. The address lines are used to identify the location of the memory storage element(s) or cell(s) to be read from or written to. The data lines contain the value of the data read or being written into the memory cells accessed. The control lines are used to direct the sequence of steps needed for the read and write operations of the DRAM.

The memory elements of a DRAM are arranged in an array of rows and columns. Each row of memory cells share a common 'word' line, while each column of cells share a common 'bit' line. Thus, the location of a memory cell in the array is the intersection of its 'word' and 'bit' lines. The number of columns of such a memory array is known as the bit width of each word.

Just like an SRAM memory cell, a DRAM memory cell uses these 'word' and 'bit' lines for its read and write operations. During a 'write' operation, the data to be written ('1' or '0') is provided at the 'bit' line while the 'word line' is asserted. This turns on the access transistor and allows the capacitor to charge up or discharge, depending on the state of the bit line.

During a 'read' operation, the 'word' line is also asserted, which turns on the access transistor. The enabled transistor allows the voltage on the capacitor to be read by a sensitive amplifier circuit through the 'bit' line. This sense circuit is able to determine whether a '1' or '0' is stored in the memory cell by comparing the sensed capacitor voltage against a threshold, i.e., 50% of the full-charge voltage. Thus, it is a '1' (charged capacitor) if the charge is still more than 50% and a '0' (discharged capacitor) if it's less than that.

For DRAMs, the simple operation of reading the data of a memory cell is destructive to the stored data. This is because the cell capacitor undergoes discharging every time it is sensed through the 'bit' line. In fact, the stored charge in a DRAM cell decays over time even if it doesn't undergo a 'read' operation. Thus, in order to preserve the data in a DRAM cell, it has to undergo what is known as a 'refresh' operation.

A refresh operation is simply the process of reading a memory cell's content before it disappears and then writing it back into the memory cell. Typically it is done every few milliseconds per word. However, the refresh cycle itself is very short (in the order of nanoseconds), since a DRAM IC contains thousands of words that need to be refreshed regularly at that interval. The need for regular refreshing gave DRAMs the name 'dynamic'.

Aside from its memory array, a DRAM device also needs to have the following support circuitries to accomplish its functions: 1) a decoding circuit for row address and column address selection; 2) a counter for tracking the refresh operation sequence; 3) a sense amplifier for reading and restoring the charge of each cell; and 4) a write enable circuit to put the cell in 'write' mode, i.e., make it ready to accept a charge.

DRAMs are mainly used as a computer system's volume memory, since they are denser and less costly than SRAM's. However, they are not suited for speed-sensitive applications such as cache memories since the dynamic refreshing required by them slows down system operation. SRAM's are a better choice if speed is a major concern.

HOME