Static Random Access Memories (SRAMs)

Random Access Memory (RAM) refers to a read/write memory device that can read data from or write data to any of its memory addresses, regardless of what memory address was last accessed for reading or writing.  RAM comes in two major classifications: Static RAM, or SRAM, and Dynamic RAM, or DRAM.

SRAMs store data in flip-flops, which retain data as long as the SRAM is powered up.  DRAMs store data in cells that depend on capacitors, which need to be 'refreshed' continuously since they are not able to retain data indefinitely even if the device is continuously powered up.

A typical SRAM IC has address lines, data lines, and control lines. The address lines are used to identify the location of the memory storage element(s) or cell(s) to be read from or written to.  The data lines contain the value of the data read or being written into the memory cells accessed.  The control lines are used to direct the sequence of steps needed for the read or write operations of the SRAM.

The memory elements of an SRAM are arranged in an array of rows and columns.  Each row of memory cells share a common 'Word Enable' line, while each column of cells share a common 'bit' line. The number of columns of such a memory array is known as the bit width of each word.

The basic storage element of an SRAM is a circuit that consists of 4 to 6 transistors. This multi-transistor circuit usually forms cross-coupled inverters that can hold a '1' or '0' state as long as the circuit is powered up.  A pair of cross-coupled inverters have the output of one inverter going into the input of the other and vice versa, such that the output (and input) of one inverter is the complement of that of the other.

This circuit doesn't need periodic refreshing or clocking in order to hold its data, making the SRAM faster than a DRAM (which needs data refreshing).  All it needs is a constant supply of power. However, since the memory cell of an SRAM is more complex than that of a DRAM, it eats up more space on the chip (which means that you get less memory per given area), making SRAM's more expensive than DRAM's.

Data is written into an SRAM's storage element by setting the 'bit' line (usually referred to as Dataj) to the data value to be written and then enabling the element's corresponding word line. Asserting the 'Word Enable' line while driving the data bit and its complement into the cross-coupled inverters of the storage element causes the data bit to overwrite the previous state of the element. If a word consists of several bits, then the whole word may be written with new data in one step if the new values are provided to all the bit lines at the same time before the 'Word Enable' line is asserted.

Reading the content of an SRAM's storage element also requires the 'Word Enable' line to be asserted.  This time, however, the SRAM uses sense amplifiers to detect the voltage difference between the voltage at Dataj and that of Dataj's complement at the outputs of the cross-coupled inverters.  If the former is greater than the latter, then the cell contains a logic '1'.  Otherwise, the cell contains a logic '0'.

One important operating parameter of an SRAM is its memory access time, which is the time needed for new data to appear at the data outputs after the new data address becomes valid. Fast SRAMs have shorter memory access times.  For more details on SRAM parameters, please see: SRAM test parameters.

Static RAM's are seldom used as a system's main RAM because of its high cost and lower memory density.  They are, however, widely used in cache applications for the microprocessor, since these are speed-sensitive applications that the SRAM is better suited for.

See Also:  What is a Semiconductor?;  SRAM Test Parameters;  DRAMs;  Microprocessors