Testing / JTAG Standard
also known as the JTAG standard, or simply
refers to the IEEE Standard 1149.1, which is a standard that defines a
set of design rules for facilitating the testing, programming, and
debugging of a semiconductor device at the chip, board, and systems
level. The acronym "JTAG" stands for
"Joint Test Action Group",
which is the consortium of North American and European companies that
defined the standard.
of various surface mount technologies for semiconductor packaging more
than two decades ago resulted in very dense board assemblies that are
difficult to test or debug at component level, mainly because of the
greater difficulty with which the components' external electrical
connections could be accessed. Furthermore, the problem only got worse
with time as surface-mount packages continued to shrink.
testing, which refers to the use of hardware, jigs, and fixtures to test
a semiconductor device by accessing its pins directly, was no longer a
practical option for 'modern' packages sprung from these newer
technologies. The need to resolve problems associated with the
testability of these surface-mount packages triggered the formation of
the JTAG in 1985, and
the subsequent definition of the boundary-scan testing standard.
testing basically involves
of special test circuits at chip level that would facilitate board-level
testing of the chip and the board itself. These additional
signals to be
into and out of the I/O circuits of a device in a
manner, letting the device to be tested with a small number of
(just 4 pins, to be exact). An industry standard since 1990, the JTAG standard is now one of
the most popular and widely-used Design for Test (DFT) techniques today.
boundary-scan testing include: 1) significant reduction in the required
number of physical test points on the board; 2) increased board
component density; 3) corresponding reduction in costs associated with
test fixtures; 4) shorter time-to-market; 5) on-board testing and
programming capabilities; 6) reduced in-circuit testing time; and 7)
higher production efficiency.
device has: 1) a
on each of its I/O pins; 2) a
or 'scan chain' that connects these boundary cells together in
manner; 3) 4 or 5
to handle the JTAG signals; 4) a
Test Access Port (TAP) for controlling
the JTAG signals used in boundary-scan testing; and 5) a 16-state TAP
that controls the states of operation of the boundary-scan testing.
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operating conditions, the boundary cells simply let the input/output
signals pass through them, into and out of the I/O pins. When the device
is placed under the
however, these boundary cells become 'active' for use in the direct
capture or control of the signals going into and out of the I/O
circuitries of the device, circumventing the device's normal input and
output connections. The boundary cells basically consist of multiplexed
shift-registers that are located around the chip's periphery (hence the
name 'boundary' cell).
access port is simply a serial interface port defined by the IEEE 1449.1
to consist of at least 4 pins (optionally 5) in a JTAG-compliant device.
These 5 pins, which are used to implement JTAG's serial protocol for
boundary-scan testing, are: 1) the TCK pin, which is a clock signal that
synchronizes the internal tap controller state machine operations; 2)
the TMS pin, which is a mode select signal sampled at the rising edge of TCK to determine the next machine state; 3) the
pin, which is the
data input pin; 4) the TDO pin, which is the data output pin; and 5) the TRST
pin (optional), which is an asynchronous reset pin.
The properties and
capabilities of a JTAG-compliant device's boundary-scan logic are
defined by an external file known as the
Language (BSDL) file. BSDL files are provided by the manufacturers
of JTAG-compliant devices for use in the definition and generation
of algorithms for the boundary-scan operation of their devices.
a device or
circuit board using boundary-scan technology may consist of the following
basic steps: 1) the external tester applies diagnostic input signals to
the input pins of the device; 2) the boundary-scan cells at the input
pins capture the input signals; 3)
the input data are scanned or serially shifted into the core via the TDI pin;
4) the resulting output data are serially shifted out of the core via the TDO
pin; and 5) the external tester compares the output data of the device
against expected results. Board defects
such as open pins, missing devices, misoriented components, or dead
devices can be found by such simple tests.
Boundary-scan technology has
also been used by some companies in software debugging
CPU's. Using proprietary techniques complemented by adequate on-chip
support, the JTAG interface was utilized to download code from a CPU,
execute it, and examine register and memory values. These
functions are enough to handle most of the low-level debugging tasks
expected from a typical software debugger. Aside from debugging, the
JTAG interface can also be used for
Electrical Testing; BIST
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