Posted by balam122: Wed Aug 17, 2005 2:05 pm    Post subject: SOIC delam

Hi,

Kindly clarify the following:
Is the occurrence of delam / crack effects based on

1. Mold compound strength
2. Mold compound type

for the same DFS tools / force?

Posted by Beengg: Thu Aug 18, 2005 6:11 am    Post subject:

Delam is more related to adhesion of molding compound to leadframe. Factors affecting this: molding compound chemistry, leadframe design, presence of contam on leadframe, package design itself, etc.

Pkg cracking is caused by many many possible factors. But if your TFS equipment is bad, then crack will occur no matter what molding compound you use. So make your set-up less stressful to pkg.

Posted by Bala: Fri Aug 19, 2005 3:34 pm    Post subject: SOIC Delamination

Hi,

Basically there is no quality issue with Mold Compound X. But when we switch to Mold Compound Y of another vendor due to cost advantage, for the same set of Dambar trim toolings, we face the issue of delamination induced crack (along the package body width and along the axis of parting line of top & bottom package) where the degating takes place. In spite of reducing the cutting clearance the issue is getting repeated but with very minor defect rate. Is there any known procedure to check a compound's "Resistance to Package crack". The Mold parameters are quite standard and we don't see the issue after molding.

But the same compound Y is performing well in other QSOP Packages (smaller lead pitch) where the punch width is lesser and the impact force in turn is lesser.

Posted by Beengg: Fri Aug 19, 2005 10:32 pm    Post subject:

Bala, did your team do a qual before releasing the new molding compound? You might want to go back to the qual report and see why the issue was not encountered that time. What's the difference then and now? For example, did the toolings get worn-out already? Bcos worn-out tools can cause delam.

Posted by Guest: Mon Aug 22, 2005 5:23 pm    Post subject:

Hi Beengg,

The compound was qualified for QSOP packages and by extension, it was qualified for SOIC packages very recently as the package dimensions are similar and the pin count was smaller. The problem got triggered only recently and since the severity of the problem was high, we increased the sample size and frequency of monitoring and found that the issue was specific to a mold compound.

However now, the mold compound supplier has confirmed that it is basically a capability issue of the compound as it is not able to withstand the cutting stress. This compound has lesser filler content and we now plan to switchover to improved versions of compound.

Thanks for your help.

regards,
Bala.