Encoders and Decoders
Multiplexing
is defined as the process of feeding several independent signals to a
common load, one at a time. The device or switching circuitry used to select and connect
one of these several signals to the load at any one time is known as a
multiplexer.
The reverse
function of multiplexing, known as
demultiplexing,
pertains to the process of feeding several independent loads with signals
coming from a common signal source, one at a time. A device used for
demultiplexing is known as a
demultiplexer.
Multiplexing and
demultiplexing, therefore, allow the efficient use of
common
circuits to feed a common load with signals from several signal
sources, and to feed several loads from a single, common signal source,
respectively.
In digital circuits, the term
'multiplexing' is also sometimes used to refer to the process of
encoding,
which is basically the generation of a digital code to indicate which of
several input lines is active. An encoder or
multiplexer is
therefore a digital IC that outputs a digital code based on which of its several
digital inputs is enabled.
On the other
hand, the term
'demultiplexing' in digital
electronics is also used to refer to
'decoding',
which is the process of activating one of several mutually-exclusive
output lines, based on the digital code present at the binary-weighted
inputs of the decoding circuit, or decoder. A decoder or
demultiplexer is
therefore a digital IC that accepts a digital code consisting of two or
more bits at its inputs, and activates or enables one of its several
digital output lines depending on the value of the code.
Multiplexing
and demultiplexing are used in digital electronics to allow several chips
to share common signal buses.
In demultiplexers, for
instance, the
output lines may be used to enable memory chips that share a
common data bus,
ensuring that only one memory chip is enabled at a time in order to
prevent data clashes between the chips.
If
a demultiplexer or decoder has
2N output lines, then it has
N input lines. A
common example of a decoder/demultiplexer IC is the 74LS138, which is a
Low-Power Schottky TTL device that has 3 input lines and 8 output lines.
Of course, a decoder IC such as the 74LS138 also has
chip control
lines that need to be 'enabled' for the decoding function to take place.
In the case of
the 74LS138, these control lines consist of one active high control line (G1, pin 6) and
two active-low control lines (G2A, pin 4 and G2B, pin 5). Thus, the
74LS138 will only be in its 'decoding' mode if G1 is at logic '1' and G2A
and G2B are at logic '0'. The 74LS138, whose generic product name is
'3-to-8 Line Decoder/Multiplexer', obeys the truth table shown in Table 1. The
outputs of the 74LS138 are
'active-low',
i.e., the enabled output goes to logic '0' while all the other outputs are
at logic '1'.
Table 1.
Truth Table for the 74LS138, a 3-to-8 Line Decoder
G1 |
G2a |
G2b |
A2 |
A1 |
A0 |
Y0 |
Y1 |
Y2 |
Y3 |
Y4 |
Y5 |
Y6 |
Y7 |
0
X
1
1
1
1
1
1
1
1 |
X
1
0
0
0
0
0
0
0
0 |
X
1
0
0
0
0
0
0
0
0 |
X
X
0
0
0
0
1
1
1
1 |
X
X
0
0
1
1
0
0
1
1 |
X
X
0
1
0
1
0
1
0
1 |
1
1
0
1
1
1
1
1
1
1 |
1
1
1
0
1
1
1
1
1
1 |
1
1
1
1
0
1
1
1
1
1 |
1
1
1
1
1
0
1
1
1
1 |
1
1
1
1
1
1
0
1
1
1 |
1
1
1
1
1
1
1
0
1
1 |
1
1
1
1
1
1
1
1
0
1 |
1
1
1
1
1
1
1
1
1
0 |
If
a multiplexer or encoder has
N output lines, then it has
2N input lines. A
common example of a decoder/demultiplexer IC is the 74LS148, which is a
Low-Power Schottky TTL device that has 8 input lines and 3 output lines.
The 74LS148 is a priority encoder, which means that if more than one of
its inputs are active, then the active input line with the highest binary
weight will be given
priority, and the output of the encoder will depend on this prioritized
input. Table 2 shows the truth table for the 74LS148. Note that E0 and GS
are output pins while E1 is a control pin (input).
Table 2.
Truth Table for the 74LS148, an 8-to-3 Line Priority Encoder
E1 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
A2 |
A1 |
A0 |
E0 |
GS |
1
0
0
0
0
0
0
0
0
0 |
X
1
0
1
1
1
1
1
1
1 |
X
1
X
0
1
1
1
1
1
1 |
X
1
X
X
0
1
1
1
1
1 |
X
1
X
X
X
0
1
1
1
1 |
X
1
X
X
X
X
0
1
1
1 |
X
1
X
X
X
X
X
0
1
1 |
X
1
X
X
X
X
X
X
0
1 |
X
1
X
X
X
X
X
X
X
0 |
1
1
0
0
0
0
1
1
1
1 |
1
1
0
0
1
1
0
0
1
1 |
1
1
0
1
0
1
0
1
0
1 |
1
0
1
1
1
1
1
1
1
1 |
1
1
0
0
0
0
0
0
0
0 |
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