components that make up the circuit on a monolithic die need to have
electrical isolation from each other in order to function. The most common
techniques used for achieving component isolation during wafer fabrication
include the following: 1) by employing reverse-biased p-n junctions; 2)
through what is known as mesa isolation; 3) by wafer bonding to an
insulating substrate; 4) by oxide isolation; 5) by trenching; and 6)
through a combination of any of these processes.
has an extremely low leakage current, which is why its use as an isolation
technique during wafer fabrication is very common. By doping two
adjacent regions with opposite types of conductivity and providing them
with adequate reverse biasing, they become effectively isolated from each
other. Under such a situation, the coupling between the regions is
only capacitive in nature, which becomes an issue only at high
somewhat obvious technique for achieving component isolation is known as
This involves the building of the components on an active film which was
grown on an insulating (or semi-insulating) film, and then etching moats
around the components. This results in the components becoming
individual 'islands', or 'mesas', hence the name 'mesa isolation' given to
this isolation technique. Circuits fabricated on silicon
on insulators, as well as those made on epitaxial GaAs over
semi-insulating (SI) GaAs substrate, are examples of applications of
insulative substrate may be considered as a variant of mesa isolation.
This isolation technique takes advantage of the fact that any two flat,
smooth, clean, and hydrophilic surfaces can be bonded at ambient
temperature without the use of external forces. Wafer bonding can be
applied to widely dissimilar materials. Once the moats are etched around
the 'mesas', isolation is provided by the insulating substrate.
As its name
techniques consist of a series of material deposition and removal steps
that leads to the formation of active single-crystal tubs that are
completely surrounded by an oxide layer. Such oxide layers, once
formed, provide near-perfect isolation between the active tubs.
is a process wherein anisotropic wet etching or reactive ion etching is
employed to dig a trench around the active region. The dug trench is
then filled up with isolating material. Planarization is done after
filling up the trenches.
Sorab K. Ghandhi, VLSI Fabrication Principles, Wiley-Interscience
Wet Etching; Dry
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