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Temperature Cycle Versus Thermal Shock

          

Reliability engineers have always asked this question.... What's the difference between Temperature Cycle Test (TCT) and Thermal Shock Test (TST)?  These two tests are easy to distinguish in terms of their respective testing equipment and specifications.  The real question is this - when should each of them be used?  Or what reliability information does one offer that the other one doesn't?  Or what failure mechanisms does one accelerate that the other one can not? These questions arise because TCT and TST are subjecting the samples to very similar stresses, with the latter just doing it at a faster rate. As such, some reliability engineers believe that the two tests are redundant, and that doing one of them is enough.  Of course, not all reliability engineers agree. The archived forum thread below raises the same question on TCT and TST.

  

Posted by Paulpang: Thu Aug 09, 2007 9:30 pm    Post subject: Package Qualification: TCT Vs. TST

 

Hi All:
For package qualification, can we perform thermal shock test under gas to gas condition but no liquid to liquid? Pls advice, much appreciated.

regards,
paul

 

Posted by zsp0911: Wed Mar 26, 2008 8:36 pm    Post subject:

 

i also want to know.~
hope someone who can help us~
thanks a lot
_________________
Peter

 

Posted by zsp0911: Tue Apr 01, 2008 9:27 am    Post subject:

 

I have check the info.
TCT and TS is the same test of temperature cycle. and the difference is TCT using gas for IC , TS using liquid for Wafer.
_________________
Peter

 

Posted by FARel Engr: Tue Apr 01, 2008 1:13 pm    Post subject:

 

In common semicon industry usage, TCT and TST are different in terms of their respective temp profiles. TCT has longer transfer and dwell times than TST, although the extreme temperatures used by both tests are generally the same. This is why TST generally employs a liquid-to-liquid stress - to meet the faster transfer and dwell times of cyclical temperature stress.

Many studies in the past have shown, however, that TCT is able to capture failures that TST is supposed to catch. In fact, some semicon engineers believe that TST is no longer necessary for most quals, i.e., performing TCT is enough.

If you're planning to drop TST from your future quals, I suggest that you do some serious correlation studies of your own to show that doing TCT is enough. That way, you'll have your own local data to show in case someone looks for supporting data that TCT and TST are basically equivalent as far as your packages/devices are concerned.

 

Posted by Paula: Wed Apr 02, 2008 11:36 am    Post subject:

 

In addition...

It actually depends on the failure mechanism that you are trying to accelerate. For example, delaminations - TCT, flipchip bumps - TST, board level BGA interconnect - TST, component level BGA - TCT... You can do both if you have the means.

      

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